The present invention generally relates to semiconductor devices, and more particularly to a semiconductor memory device fabricated according to a submicron design rule. Particularly, the present invention relates to a dynamic random access memory that has a storage capacity of 256 Mbits or more.
The dynamic random access memories (DRAMs) are characterized by the simple device structure in that the device typically includes only a single memory cell capacitor for storing information and a single transfer gate transistor connected to the memory cell capacitor. Thus, the device can be fabricated easily with a large integration density and is suitable for constructing a semiconductor memory having a large storage capacity. Currently, the devices having a storage capacity of 256 Mbits or 1 Gbits are studied intensively.
In order to fabricate the large-scale DRAMs having a large number of memory cells assembled therein, various efforts have been made so far. Such efforts of course include the development of the submicron patterning processes that are applicable to the fabrication of the DRAMs having extremely minute memory cells. Particularly, the development of optical lithography applicable to the submicron patterning is essential for the mass production of DRAMs.
Simultaneously, a considerable effort has been devoted for securing a sufficient capacitance for the memory cell capacitors while reducing the size of the memory cells simultaneously. It should be noted that the reduction in the size of the memory cell capacitor generally invites a reduction in the capacitance of the memory cell. In the DRAMs, the capacitance of the memory cell capacitors is required to be larger than the parasitic capacitance of the bit lines by a predetermined factor.
More specifically, the total electric charges that are stored on a bit line as well as in a memory cell capacitor cooperating with the bit line are represented as EQU C.sub.B .multidot.V.sub.B +C.sub.S .multidot.V.sub.S =(C.sub.B +C.sub.S).multidot.V, (1)
where C.sub.B represents the capacitance of the bit line, C.sub.S represents the capacitance of the memory cell capacitor, V.sub.B represents the bit line voltage in the state that the transfer gate transistor which connects the memory cell capacitor and the bit line is turned off, V.sub.S represents the voltage on the memory cell capacitor, and V represents the bit line voltage in the state that the transfer gate transistor is turned on. Using the above relationship, the voltage change .DELTA.V that appears on the bit line in response to the turning-on and turning-off of the transfer gate transistor is represented as EQU .DELTA.V=V-V.sub.B =(V.sub.S -V.sub.B)/(1+C.sub.B /C.sub.S).(2)
It should be noted that this voltage change .DELTA.V is detected by the sense amplifier that typically has a flip-flop construction. In order to achieve a reliable reading, it is necessary to maximize the voltage change .DELTA.V, and for this purpose, it is necessary to set the capacitance C.sub.S of the memory cell as large as possible as compared with the parasitic capacitance C.sub.B.
In order to maximize the capacitance C.sub.S in the memory cells that are fabricated in accordance with the submicron design rule, the inventor of the present invention has previously proposed a memory cell wherein the memory cell capacitor has a stacked structure (T. Ema, Technical Proc. SEMICON/JAPAN 1990, pp.184-193). In this proposal, the memory cell capacitor is formed into a stacked fin structure wherein a number of thin electrodes are stacked with each other with a thin dielectric film interposed therebetween. Further, the memory cell has the so-called shielded bit line structure (SBL) wherein an electrode plate is provided above the memory cell capacitor to extend over the bit line as an opposing electrode of the capacitor. Thereby, the capacitance of the memory cell capacitor is increased significantly with the increased surface area, without increasing the height or aspect ratio of the memory cell capacitor.
FIG. 1 shows the relationship between the aspect ratio and the design rule represented in terms of the storage capacity of the DRAM, for a device having the stacked fin structure in the memory cell capacitor, in comparison with a device that has an ordinary structure for the memory cell capacitor. In both the stacked fin memory cell capacitor and the ordinary memory cell capacitor, a capacitance of 25 fF is assumed. The aspect ratio is defined as a ratio of the height (h) of the memory cell capacitor divided by the spacing (f) between the memory cells. From FIG. 1, it will be noted that the aspect ratio of the stacked fin memory cell capacitor remains substantially the same when the design rule has been changed from 4 Mbits to 64 Mbits. On the other hand, the aspect ratio of the ordinary memory cell capacitor increases steeply when the design rule has been changed such that the storage capacity increases beyond 4 Mbits.
FIG. 1 further indicates that the aspect ratio starts to increase steeply even in the stacked fin memory cell capacitor, when the storage capacity is increased beyond 256 Mbits. With the increase of the aspect ratio, it will be noted that height of the memory cell capacitor generally increases. Such an increase of the height of the memory cell capacitor occurs inevitably in the DRAMs of high integration density wherein further reduction of the spacing between the memory cells is difficult.
FIG. 2 shows such an increase of the height of the memory cell capacitor. In this case, too, a capacitance of 25 fF is assumed for the both types of capacitors. From FIG. 2, it will be noted that the height of the memory cell capacitor decreases suddenly at 16 Mbits in correspondence to the employment of the stacked fin structure. With further increase in the strictness of the design rule, the height of the memory cell capacitor increases steeply as indicated in FIG. 2. This means that the memory cell array region of the DRAM has a substantially increased height as compared with the peripheral region where the peripheral devices such as decoders, sense amplifiers, input/output buffers, etc. are provided.
In such a memory device having a substantial step height between the memory cell array region and the peripheral region, it will be noted that the exposure of the conductor pattern that extends between the memory cell array region and the peripheral region is difficult, particularly when an optical exposure system having a large numerical aperture (N.A.) is employed. It should be noted that a large numerical aperture is essential for the optical exposure system for achieving the exposure with high resolution, while such a large numerical aperture simultaneously invites a substantial reduction of the focal depth. In other words, the high resolution optical exposure system that is employed for the photolithographic patterning process of the DRAMs generally has an extremely limited focal depth, and the simultaneous exposure of the conductor pattern on the memory cell array region and the conductor pattern on the peripheral region is impossible. This in turn means that the exposure of the conductor strips that extend continuously between the memory cell array region and the peripheral region is totally impossible. It should be noted that the formation of such a conductor pattern is essential in the ASIC chips wherein a memory cell array and a logic device are assembled on a common chip surface.
In FIG. 2, the focal depth of the optical system that is used for fabricating the device is also illustrated. As can be seen in the drawing, the focal depth decreases generally linearly with the increased integration density and intersects with the curve that represents the height of the memory cell capacitor. In FIG. 2, the focal depth is drawn with the same scale as the height of the memory cell. It should be noted that in the region where the focal depth is larger than the step height, the exposure of the device can be achieved without problem. On the other hand, when the line representing the focal depth intersects with the curve representing the step height, the exposure becomes difficult. This problem becomes conspicuous at the design rule of 256 Mbits to 1 Gbits.
The foregoing results of FIGS. 1 and 2 indicates that even when the stacked fin memory cell capacitor is employed in combination with the shielded bit line structure, there appears a limitation in the miniaturization at the storage capacity of about 256 Mbits. The fabrication of the device having an integration density exceeding this limit is generally impossible, as long as such a conventional device structure that requires the large size memory cell capacitor is employed. This in turn indicates that, in order to realize a DRAM that has the storage capacity exceeding the foregoing limit, it is inevitable to reduce the height and hence the size of the memory cell capacitor.
Conventionally, it is known that the capacitance of a dielectric capacitor can be increased when the thickness of a dielectric film that forms the capacitor is decreased. Thus, one may think that the necessary capacitance may be secured even when the height of the memory cell capacitor is reduced, provided that the thickness of the dielectric film formed on the electrode fins is reduced.
FIG. 3 shows a relationship between the thickness of a dielectric film and a maximum voltage that can be applied across a pair of electrodes that form a capacitor, with the dielectric film interposed therebetween. There, the thickness of the dielectric film is represented in terms of the thickness of a silicon oxide film, while the actual measurement was made for a composite film of silicon oxide and silicon nitride. In FIG. 3, the open circles represent the result for the case wherein the silicon nitride film having a thickness of 60 .ANG. is oxidized with various lengths of the oxidation process. On the other hand, the solid circles represent the result for the case wherein a silicon nitride film having a thickness in the range between 60 .ANG. and 85 .ANG. is oxidized for a predetermined duration. It should be noted that the relationship represented in FIG. 3 corresponds to the condition wherein a leak current of 10.sup.-8 /cm.sup.2 flows through the dielectric film. It should be noted that this level of 10.sup.-8 /cm.sup.2 defines the upper tolerable limit for a memory cell capacitor to retain the information stably.
Referring to FIG. 3, it will be noted that the voltage corresponding to the foregoing leak current of 10.sup.-8 /cm.sup.2 decreases generally with decreasing thickness of the dielectric film. On the other hand, it should be noted that the leak current flows through the dielectric film even when the voltage is reduced to zero, when the thickness of the dielectric film is reduced below about 35 .ANG.. It should be noted that such a leak current flows due to the direct tunneling effect of the electrons. In other words, the result of FIG. 3 indicates that the physical law prohibits the reduction of the thickness of the dielectric film below several nanometers. When a supply voltage V.sub.CC of 3.3 volts is assumed, the thickness of the dielectric film cannot be reduced below 50-60 .ANG..
In designing the memory cell capacitor, it is further necessary to keep in mind the lower limit of the thickness of the polysilicon layer. When the thickness is smaller than 50-100 .ANG., it is known that the polysilicon layer cannot be grown uniformly. Assuming the thickness of the polysilicon layer of 50 .ANG. and the thickness of the dielectric film of 50 .ANG., it should be noted that the thickness of a single fin electrode has to be larger than 20 nm (=5 nm+2.times.5 nm+5 nm). When the tolerance for fabrication is taken into consideration, it is preferred that the fin electrode has a thickness of 30 nm or more. When such an electrode fin is stacked for securing sufficient capacitance, the height of the memory cell capacitor increases inevitably.
In such a situation, it is inevitable to reduce the capacitance of the memory cell capacitor in order to realize the DRAMs that have the storage capacity exceeding 256 Mbits. However, there is a limitation in the reduction of the capacitance of the memory cells as already noted with reference to Eqs. (1) and (2).